Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow is hardware description language (HDL) compilation. HDL compilation involves performing synthesis, clock allocation, placement, routing, and timing analysis of the system on the target device.
Register retiming is a circuit optimization technique that may be utilized during HDL compilation to improve the performance of sequential circuits. Register retiming repositions registers (flip-flops) in the circuit without changing the combinational logic of the circuit.